Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fifo fpga

Search list

[ARM-PowerPC-ColdFire-MIPS] FPGA

Description: 实现USB的slave FIFO功能的FPGA部分-Implementation of USB slave FIFO
Platform: | Size: 84992 | Author: hugd | Hits:

[VHDL-FPGA-Verilog] fifo

Description: CAN总线，DSP+FPGA+SJA1000架构，FPGA负责逻辑设计,此文件内有FPGA负责dsp和sja1000通信-CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
Platform: | Size: 4096 | Author: 张浩阳 | Hits:

[File Format] Altera-FIFO

Description: 介绍了Altera的FPGA的FIFO的功能与介绍-Introduction of Altera' s FPGA capabilities with the introduction of the FIFO
Platform: | Size: 701440 | Author: 王兵兵 | Hits:

[SCM] fifo

Description: 利用stm32f407作为测试板，利用IO和精确的延时（这个延时方式任意）来模拟FIFO时序来达到和FPGA的FIFO模块进行通信。测试时用的是Altera的FPGA的FIFO模块。-Stm32f407 use as a test board, the use of IO and accurate delay (the delay in any way) to simulate FIFO timing to achieve and FPGA FIFO module to communicate. When the test is used in Altera' s FPGA' s FIFO module.
Platform: | Size: 1024 | Author: 龙鸿峰 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FPGA TI DSP的EMIF接口的地址总线问题-FPGA FIFO
Platform: | Size: 2849792 | Author: liuky | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
Platform: | Size: 135168 | Author: seer | Hits:

[MPI] FIFO

Description: FIFO读写操作，quartusII VHDL IP FPGA-FIFO VHDL IP FPGA
Platform: | Size: 100352 | Author: eclipseds5 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
Platform: | Size: 145408 | Author: 陈陈陈啊 | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: FPGA利用串口、FIFO实现串口收发数据(FPGA using serial port, FIFO serial transceiver data)
Platform: | Size: 196608 | Author: mzl127 | Hits:

[VHDL-FPGA-Verilog] CCD_Array

Description: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
Platform: | Size: 3320832 | Author: muralidh | Hits:

[VHDL-FPGA-Verilog] parameter_uart_rx

Description: 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.)
Platform: | Size: 4096 | Author: 老工程师 | Hits:

[VHDL-FPGA-Verilog] syn_dp_fifo.v

Description: 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
Platform: | Size: 1024 | Author: junkaizhan | Hits:

[VHDL-FPGA-Verilog] SDRAM缓冲测试程序

Description: 对FPGA的SDRAM进行测试，主要是实现FIFO-SDRAM-FIFO的数据传输(Test the SDRAM of the FPGA)
Platform: | Size: 76057600 | Author: 降落 | Hits:

[VHDL-FPGA-Verilog] 20170808_fifo_xc5v_v1.5

Description: FPGA通过fifo进行数据的载入载出，实现数据的暂时存储和传递(FPGA through fifo data loading and unloading, to achieve temporary storage and delivery of data)
Platform: | Size: 10388480 | Author: bingbinglong | Hits:

[VHDL-FPGA-Verilog] eetop.cn_FIFO_Buffer

Description: 异步FIFO的Verilog程序及其测试程序(FPGA/Verilog FIFO_ASYN)
Platform: | Size: 68608 | Author: 半岛铁盒 | Hits:

[VHDL-FPGA-Verilog] tx_rx_fifo

Description: 通过串口将接收到的数据存入fifo,fifo存满后使能串口发送功能，将接收到的数据发送出去(Use fifo to realize the receive and send function of the uart. The function is no problem.)
Platform: | Size: 3791872 | Author: Pgaf | Hits:

[USB develop] 13_usb_test

Description: READ 16BIT DATA FROM EP2 FIFO AND SEND TO EP6 FIFO
Platform: | Size: 1006592 | Author: ZHOUHAIJUN | Hits:

[VHDL-FPGA-Verilog] fifo_test

Description: fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
Platform: | Size: 1957888 | Author: dufanbao | Hits:

[Books] Clifford_E._Cummings经典论文合集

Description: FPGA中经典模块的实现相关介绍文档，经典(FPGA in the classic module of the implementation of the document, the great God of foreign papers)
Platform: | Size: 2029568 | Author: gxgone | Hits:

[Com Port] tx_interface_project

Description: 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
Platform: | Size: 850944 | Author: lionel_messi | Hits:
« 1 2 3 4 5 6 7 89 10 11 12 13 14 »

CodeBus www.codebus.net